It is generally desirable to make memory cells as small as possible so that more memory cells can be integrated into each chip. Higher capacitance storage capacitors can also provide better definition when reading the memory cell, lower soft error rate, and enable lower voltage operation. Therefore, if memory cells can be made smaller and with higher capacitance, semiconductor memory devices can become more highly integrated.
Capacitors having three-dimensional structures have been proposed in an attempt to increase cell capacitance. These types of capacitors usually have a lower electrode in the shape of a fin, a box, or a cylinder. However, the manufacturing processes for forming capacitors with three-dimensional electrode structures may be complicated and defects may be easily generated during the manufacturing processes. Accordingly, research into the use of high dielectric materials for increasing the capacitance of capacitors is actively being conducted to avoid the need for forming capacitor electrodes having three-dimensional structure. Similarly, the use of thin dielectric materials having stable dielectric characteristics are also being considered.
Unfortunately, high dielectric materials such as tantalum pentoxide (Ta.sub.2 O.sub.5) have reduced dielectric strength when formed as relatively thin layers. For example, whereas bulk tantalum pentoxide may have a dielectric constant in a range between about 22 and 25, thin tantalum pentoxide layers having thickness in a range between about 50 A and 100 A may only have dielectric constants at levels of about 5-6 when used as capacitor dielectric material. This reduction may be due to the formation of a thin natural oxide layer at an interface between a capacitor electrode and the tantalum pentoxide layer. This thin natural oxide layer reduces the net dielectric constant of the resulting composite dielectric layer containing both the natural oxide layer and tantalum pentoxide layer. This tantalum pentoxide layers may also have relatively poor leakage current and breakdown characteristics. Conventional techniques for forming integrated circuit capacitors having tantalum oxide dielectric layers are described in an article by K. W. Kwon et al., entitled "Ta.sub.2 O.sub.5 /TiO.sub.2 Composite Films for High Density DRAM Capacitors", Technical Digest of the 1993 VLSI Technology Symposium" and in U.S. Pat. Nos. 4,734,340, 5,111,355 and 5,142,438.
Notwithstanding these conventional techniques, there continues to be a need for improved methods of forming integrated circuit capacitors having high dielectric strength and reduced leakage current characteristics.